1. Field of the Invention
This invention relates generally to the fabrication of integrated circuits and more particularly to providing an improved substrate for enhanced transistor operation by growing one or more argon doped epitaxial layers upon a bulk semiconductor substrate.
2. Description of the Related Art
MOS ("metal oxide semiconductor") transistors are the basic building blocks of integrated circuits. Fabrication of MOS transistors is well known. Generally speaking, MOS transistors are manufactured by placing undoped polycrystalline silicon ("polysilicon") over a relatively thin gate oxide. The polysilicon material is then patterned to form a gate conductor directly above a channel region of the substrate. A dopant species is implanted into the gate conductor and regions of the substrate exclusive of the channel region, thereby forming source and drain regions adjacent to and on opposite sides of the channel region. For a p-type substrate, an n-type dopant is used for source and drain regions, and the resulting transistor is an NMOS ("n-channel") transistor device. Conversely, for an n-type substrate, the dopant species is p-type, and the resulting transistor is a PMOS ("p-channel") transistor device. Integrated circuits may utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate.
Complementary MOS ("CMOS") circuits are one class of devices featuring both p-type and n-type MOS transistors on the same substrate. CMOS technology is prevalent in VLSI design because it offers a lower power alternative to either PMOS or NMOS circuits. Several CMOS structures have been used to allow PMOS and NMOS transistors to share a common substrate including p-well, n-well, twin tub, and silicon on insulator ("SOI"). In a typical n-well CMOS fabrication, the starting point is a lightly doped p-type substrate. An n-well region is created in the p-type substrate by implantation or deposition and diffusion. Implantation is used to form shallow wells appropriate for fine dimension processes. Since implantation of the n-type species does not generally position the implant to the desired depth, a subsequent high temperature cycle is needed to drive the impurities to the required depth. Redistribution of the well dopant proceeds both vertically and laterally. The lateral spread determines the spacing between the well and other structures. Lateral diffusion increases for deeper implants, which is one reason why shallow well implants are utilized for fine line geometries. After well formation, the remaining steps in a CMOS process flow are similar to normal NMOS and PMOS fabrication techniques. Namely, p-channel devices will be built in the n-well, and n-channel devices will be built in the p-substrate.
One problem shared by all MOS transistor devices is unwanted impurity diffusion. As is well known in the art, impurities are used to augment carrier transport and electrical performance in transistors. Controlled diffusion of impurities can be an important step in a process flow. Thus, thermal diffusion is often required subsequent to ion implantation in order to activate the dopants and repair lattice damage. However, unwanted migration or diffusion can occur during processing or transistor operation that degrades performance. For example, consider a CMOS device with a p-type substrate having a PMOS transistor formed in an n-well. A common p-type impurity for doping the substrate is boron, which is the fastest diffusing of the substitutional impurities. During various thermal cycles in the CMOS process flow, unwanted diffusion of boron from the substrate may occur, which inhibits device performance.
Another common problem encountered in transistors and CMOS devices is punchthrough. While in operation, transistors that have heavily doped source and drain regions arranged laterally adjacent the gate conductor often experience a problem known as punchthrough, which can lead to an undesirable increase in the subthreshold current, I.sub.Dst. Punchthrough occurs when the voltage on the drain is increased with respect to the source, leading to a widening of the depletion region around the drain. The drain depletion region may eventually merge into the source depletion region, thereby reducing the potential energy barrier of the source-to-body junction, or the source-to-well junction for a transistor formed in a well. As a result, more majority carriers in the source region will have sufficient energy to overcome the barrier, causing an increased source-to-body current flow. For a device formed in a well, the increase would be in the source-to-well current flow. Collection of some of this current by the drain leads to an increase in I.sub.Dst. Likewise, vertical punchthrough can occur if the depletion region of the source/drain-to-well junction were to contact the depletion region of the well-substrate junction.
To prevent short-channel devices from entering punchthrough, the substrate doping may be increased to decrease the depletion-layer widths extending into the substrate. For many long-channel devices, a single implant may serve as both a punchthrough stop and a V.sub.T adjust. In cases where a single implant is inadequate, such as in submicron MOS transistors, a second, deeper implant may be provided. The punchthrough stop may be implanted such that its peak concentration is located at a depth near the bottom of the source and drain regions. This additional doping advantageously reduces the lateral widening of the drain depletion region below the substrate surface.
More advanced transistors and CMOS devices have been achieved by reducing device geometries, such as channel length and source/drain depth. Commensurate with minimizing device dimensions is the need for lower values of V.sub.T, the threshold voltage. As a result, punchthrough creeps up to the V.sub.T region of the silicon. This in turn translates into scaling down the depth of the punchthrough stop. However, the proximity of the punchthrough stop to the V.sub.T region may lead to an increase in V.sub.T, which is undesirable in modem devices. The competition between the desire to scale down device dimensions versus the need to inhibit punchthrough effectively limits the degree of scaling possible with known techniques. Therefore, it would be highly desirable to reduce punchthrough effects in transistors in a manner that does not limit scaling of device dimensions. This would allow the formation of shallower wells by preventing vertical punchthrough, and simultaneously allow smaller values of V.sub.T to maximize device performance.
Transistors and CMOS devices can also be fabricated using a silicon substrate having an epitaxial layer on the upper surface of the substrate. Epitaxy is a method of growing a single crystal thin film on the surface of a single crystal substrate. Currently, both n-epi on n.sup.+ substrates and p-epi on p.sup.+ substrates are utilized, with each method having advantages and drawbacks. Because of problems with n-epi on n.sup.+ substrates tend to be more serious, p-epi on p.sup.+ substrates is more widely used. The major limitation of the latter approach is that the diffusion of boron from the p.sup.+ substrate is much more severe than in the case of n-epi on n.sup.+. Thus, according to conventional CMOS technology, the thickness of the epitaxial layer is greater than the well depth since the dopants in the heavily doped substrate under the epitaxial layer diffuse toward the surface as the well dopants are diffused toward the bulk. These diffusion effects are taken into account by using a thicker p-epitaxial layer so that the bottom of the well is eventually located adjacent to the upper surface of the heavily doped substrate. It would be advantageous to have a CMOS transistor with a thinner epitaxial layer.